Moto: Wireless needs reconfigurable compute fabric

By John Walko and Loring Wirbel
iApplianceWeb
(03/25/03, 02:04:12 AM EDT)

Dallas, Texas -- At its Smart Networks Developers Conference here, Motorola Inc.'s Semiconductor Products Sector has taken the wraps off of a new Reconfigurable Compute Fabric (RCF) technology targeted at the baseband portion of next-generation wireless infrastructure gear.

RCF is at the heart of an aggressive strategy to increase the flexibility and lower the costs of the baseband portion of next-generation wireless-infrastructure gear. The first products are scheduled for release in June.

Motorola's RF and DSP Infrastructure Systems Division will for the first time demonstrate the development tools and test silicon behind the RCF technology. Separately, two Motorola groups will show reference designs based on development environments from Motorola's embedded-software subsidiary, Metrowerks Inc. The Smart Gateway 857 integrated access device reference design aims at promoting residential gateways based on digital subscriber line ports. The other reference design is for packet telephony gateway tasks in corporate PBXes and small-carrier aggregation points.

Based on an array of optimized processing elements, RCF technology offers a cost-effective, programmable alternative to ASIC- and FPGA-based baseband design, said Arif Ahmed, strategic-marketing manager of the RF and DSP infrastructure systems group. Each compute element in the array supports a limited, yet rich, instruction set, he said. Elements are connected through a flexible, high-bandwidth interconnect fabric.

"We believe our customers face a real dichotomy when it comes to baseband processing, one that affects flexibility and scalability," Ahmed said. "DSPs are fine for symbol-rate processing, but something else-something more flexible and cost-effective-is needed for chip-rate processing. Our solution is aimed at solving this problem."

The RCF technology, combined with the MSC810x StarCore DSPs, has initially been applied for baseband processing as a flexible solution to issues such as equalization, chip rate and symbol rate, and for deploying third-generation cellular (3G) functions such as smart antennas and multiuser detection. But Motorola believes it has potential in areas such as echo cancellation, video processing and MPEG-4 encode/decode.

The core architecture for the RCF device is licensed from closely held intellectual-property provider Morpho Technologies (Irvine, Calif.), which developed the reconfigurable DSP technology. The MorphoSys architecture enables 3G handsets to adapt on the fly to the different flavors of native air interfaces deployed. Motorola took a minority stake in Morpho last October.

Unlike ASICs and FPGAs, RCF does not require HDL coding and is fully programmable in C and assembly languages, Ahmed said. Metrowerks will offer its CodeWarrior integrated development environment for the reconfigurable technology.

The residential-gateway reference design uses the MPC857-DSL PowerQuicc alongside the MPC180 security processor. DSL access is based on the Alcatel ADSL chip set; four switched Ethernet ports are provided for local LAN switching functions. For voice-over-Internet Protocol (VoIP) applications, an optional card combines the 56L307 DSP with multiple codecs and subscriber-line interface circuits for four channels of analog phone service. Another optional PCMCIA card provides 802.11 wireless LAN service, using the Intersil WLAN chip set.

Motorola will offer the design as a standalone reference board or as a full platform with CodeWarrior, the Creation Suite acquired from Lineo and the WireTap tool. Dedicated Metrowerks packages are provided for an Ethernet router with firewall, Ethernet router with virtual private networking, and DSL router with either the firewall or VPN option. The basic evaluation board is priced at $1,000, the VoIP board at $5,000 and the WLAN card at $495.

Meanwhile, the packet-telephony reference platform for VoIP aggregation functions consists of a primary board and two mezzanine boards for IP-telephony gateway applications. The baseboard uses an MPC8260 processor for control-plane duties, while voice aggregation is performed on a separate daughtercard with six MSC8101 DSPs, arbitrated by an on-board FPGA.

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