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Java CPU/SRAM combo aims at cellular, iAsBy Rick Merritt
The NanoAmp plan emerges at a time when several chip makers are moving toward merging logic and memory dice in a single package and Java hardware acceleration is just beginning to find its way into cellphones, through various forms of integration. "Many people are looking at combinations of memory and logic in system-in-package products. It's a very exciting area now," said Morry Marshall, vice president of strategic technologies at market watcher Semico Research Corp. (Scottsdale, Ariz.).
Samsung Electronics announced Feb 4 a cellular applications processor, combining an ARM core, 256 Mbits of NAND flash memory and 256 Mbits of SDRAM. The S3C2410 is part of a packaging trend that will result in cell phones with powerful and flexible combinations of computing and communications capabilities, Marshall said.
Intel Corp. has also released versions of its XScale processor packaged with a flash die.
As for Java hardware acceleration in the cellphone, "no one I know of is doing it yet. They are all using software. But we are working with one major Asian manufacturer who will release a handset later this year," said Tim Rahrer, director of technology at Zucotto Wireless Inc. (San Diego), a Java processor designer.
That handset maker is integrating Zucotto's Java processor as a block on another chip in the system, he added.
Another competitor, Nazomi Communications (Santa Clara, Calif.) said it has several unannounced design wins for its JA108 accelerator that will emerge in phones starting in April. Some of those design wins are for its cores integrated with flash and SRAM in multi-chip packages similar to what NanoAmp is promising, said Jay Kamdar, chief operating officer of Nazomi.
For its part ARM Ltd. has integrated its Jazelle Java acceleration technology with its processor core. OEMs using chip sets based on the ARM926EJ will be announced soon, said Steve Steele, Java program manager at ARM.
The 104 MHz NanoAmp core is a new design that natively executes Java bytecodes, said Ron Stein, a senior marketing manager at NanoAmp. It should be 20 times faster than a software Java virtual machine and six times faster than the ARM Jazelle approach, he estimated.
The NanoAmp core sports 4 Kbytes data and 4 Kbytes instruction cache and a 64 32-bit word variable cache. The core is made at United Microelectronics Corp. in a 180-nm process. It executes most Java bytecodes in a single cycle, Stein said.
NanoAmp expects to see first silicon of the core in mid-February. It hopes to turn over cores to flash and packaging partners in March. It will take another eight weeks for those partners to design and validate multi-chip packages using the core.
Stein said NanoAmp has some flash and packaging companies signed up to make the combo parts, but would not release any names until this summer.
The Java core links to the host processor via a modified version of a typical 16-bit asynchronous memory interface
NanoAmp dubbed Moca-J (for Memory Oriented Coprocessor Acceleration for Java).
The MOCA interface is based on a pass-through mechanism. The host CPU has immediate pass-through access to memory any time it needs it without cycle delay, Stein explained.
When the coprocessor is executing, the MOCA interface feeds the host instructions to keep it occupied in a polling loop monitoring the status of the coprocessor. The coprocessor detects host pass-through requests by changes to the chip select lines, at which time it aborts any operation in process until the host returns to its idle state. When the host returns to its idle state, the coprocessor resumes from where it aborted, Stein added.
NanoAmp hopes to use the Moca-J interface for other logic functions such as security or multimedia accelerators in the future.
NanoAmp is a 40-person private company with a portfolio of about a dozen memory devices including one now in use in Vice President Dick Cheney's pacemaker. The company has foundry arrangements with UMC, ProMOS and Semiconductor Manufacturing International Corp. in Shanghai.
Designs coming
Analysts expressed mixed views about the outlook for Java chips. "I haven't seen a successful Java accelerator yet," said Will Strauss, of market watcher Forward Concepts (Tempe, Ariz.).
Markus Levy, senior analyst with In-Stat/MDR, said he is not aware of any cellphone design wins for Java chips, however, "I think they are coming," he said.
The EEMBC consortium (El Dorado Hills, Calif.) will announce a Java benchmark suite at the 3GSM World Congress beginning on Feb 19. It expects to publish the first Java chip benchmarks a month or two later, said Levy who also heads that group.
Several companies offering Java hardware or software have joined the consortium to support that work, he added.
"People are excited to see this [benchmark] happen, and that's one sign there's life in this space," Levy said.
In addition, Levy noted at least two new players are entering the Java chip fray. Multiplicity (Tel Aviv) claims it has a parallel processing chip technology to boost Java processing four-fold while cutting power consumption by half. Two senior engineers formerly of DSP Group founded the company in 2001.
It is designing Jmap1, a Java hardware accelerator optimized for J2ME, and CoreUpgrade a technology to bolster parallelism in existing system-chip designs without altering the chip's software or instruction set.
Separately, design house Octera (San Diego) said it has designed a low-end, 25,000-gate Java processor for industrial control applications that is now in final verification. The company plans a family of Java chips based on the design, some of which could have capabilities, such as support for dynamic loading of class libraries, which would make it suitable for use in cell phones.
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