Toshiba uses SoC 'platform' in consumer, networking

By Peter Clarke, SBN
iApplianceWeb
(01/31/03, 06:10:11 PM EDT)

SAN JOSE, Calif. -- Faced with shrinking time to market requirements and the emergence of small footprint embedded networking anc consumer iappliance designs, Toshiba America Electronic Components Inc. is shifting from a board level to an ARM-based system-on-chip (SoC) platform methodology.

With a series of SoC 'platforms' for complex chip design it is launching in a system it calls SoCMosaic, the company that it can reduce time-to-market to as little as six months, thereby saving millions of dollars in development costs, critical factors in the economically devastated networking market and the cost sensitive consumer space.

TEAC also said that it is partnering with six other companies are part of an intellectual property (IP) partner program that would contribute to SoCMosaic: Denali Software Inc., GDA Technologies Inc., Mentor Graphics Corp. Sonics Inc. and Synopsys Inc. The initial SoCMosaic platforms are to be based on ARM cores.

The approach has similarities to the Nexperia platform design-style of Philips Semiconductors (see June 3 2002 story ), although while Nexperia has been used internally within Philips, SoCMosaic is intend to augment Toshiba's ASIC and customer-designed chip offerings.

SoCMosaic is expected to allow rapid customization of complex system-on-chip designs by imposing the discipline of using pre-tested commodity hardware IP blocks, standardized bus interfaces and bus system, a register-transfer level (RTL) testbench and high-level, cycle-accurate C simulation.

"By using a configurable IP platform, pre-verified and pre-tested IP and support for common bus interfaces, SoCMosaic custom chip can slash total design time from a typical 18 months to as little as four months," said Richard Tobias, vice president of the ASIC and foundry business unit at TAEC, in a statement.

System level support includes hardware and software design (with firmware and middleware) running on cycle-accurate system-level models for early development of application software. TAEC intends to be active partners with its customers at the system design level, engaging with them early in the design process and delivering software and silicon.

Tobias said that he was targeting system companies developing board-level products that were looking to add features to their end-products to increase market share or reduce system cost through SOC integration. He explained that many of those companies lacked internal design resources or the specialized skill sets needed for complex SOC design. Likely customers also include system companies temporarily without the means to do yet another chip design project.

The SoCMosaic custom chip IP platform supports standard operating systems such as Linux and other real-time operating systems, contains common peripheral functions as commodity IP blocks, including I/O, interrupts, counters and serial ports plus processor cores. Customers then select differentiating IP such as embedded DRAM, and higher level system interfaces such as Ethernet, USB, 1394, PCI controllers, SerDes and optimized hardware/software application function such as VoIP, MPEG and 802.11 from Toshiba's library of software intellectual property. Toshiba also offers a range of analog IP with several variants to each IP block to meet various design requirements, such as high-speed, low-power, small area or low noise, the company said.

Toshiba expects to provide extensive help by way of hardware simulation and have software services teams works concurrently with hardware development for software driver and API adaptation, RTOS implementation and standardized middleware solutions. On-chip specialized hardware supports software debugging. The resulting hardware/software working model allows the design to be validated and tested before implementation.

The SoCMosaic platform is provided as soft RTL code that is synthesizable into multiple process technologies including 0.18-micron, 0.13-micron, 90 nanometer or 65nm process technologies, the company said.

TAEC expects to announce general availability of the first SoCMosaic custom chip platform in April 2003. The V.1 platform is aimed at embedded applications that will combine application-specific support with a single control processor running Linux or an RTOS in low-end networking and consumer applications. Customer sample shipments are expected to begin the second quarter of 2003. SoCMosaic custom chip platform V.2 will add support for multiple processor cores and high-throughput multimedia and high-end networking systems. V.2 is in development with availability expected the second half of 2003.

For more information on this story, go to www.toshiba.com.

But for instant access to more informationabout the issues, products and technologies mentioned in this story, click on the flashing icon in the upper right hand column on any page on this site. It will take you to an alternate view of iApplianceWeb based on an associatively-linked XML/Java Web map that can be used to search for any topic published here over the last 12 months.

This map allows any story on the site to be accessed by date, by category, by title, or by keyword, with results displayed within seconds either as a list of possible hits or with specific Web pages displayed below the map, which is adjustable depending on the number of hits and the number of links.

For technical article coverage, go to the  iAppliance Web Views  page and access the EETimes In Focus maps there to browse or quickly search for all articles on a particular topic since the beginning of 1998.