Echelon preps 2nd Gen power line transceivers

By Loring Wirbel
iApplianceWeb
(01/15/03, 10:51:40 PM EDT)

SAN JOSE, Calif. - Echelon Corp. will sample transceivers based on its second-generation dual-frequency narrowband technology in the first half of this year that enable data transmission over power lines.

The PL 3120 and PL 3150 will both feature the Neuron core - a control architecture used in Echelon's first-generation narrowband products and in its older spread-spectrum power line processors.

Since its first LONworks products were released in 1990, Echelon has focused on low-data-rate power line networks for home automation and industrial control, rather than on broadband transmission over power lines. Director of marketing Steve Nguyen said that Echelon carefully considered adding broadband devices to its product mix, but decided there were too many reliability problems still associated with power line transmission at high data rates. The new chips continue Echelon's focus on 7-kbit/second applications operating at 10 MHz.

Echelon's narrowband architecture uses 132 kHz as a primary frequency, with automatic switching to a 115-kHz frequency when the primary frequency is blocked. The new chips feature a patented error-correcting algorithm and an on-chip output amplifier for improved reliability. The chips support the more stringent band limitations of the European Union as well as FCC-based regulations for U.S. networks. By changing crystals, the chips can support either European A or C band networks.

Both transceivers include a Neuron core, DSP functions and D/A front-end converter functions. The PL 3120 has on-chip memory appropriate for smart meters and actuators; it includes 4 kbytes of EEPROM, 2 kbytes of RAM, a task scheduler, I/O drivers, and a ROM-based implementation of the ANSI 709.1 device networking protocol.

The PL 3150 is intended for residential gateways and home automation applications where larger off-chip memory is required. It has 0.5 kbytes of EEPROM, 2 kbytes of RAM, and an external memory bus that allows the addressing of up to 64 kbytes of off-chip memory.

Echelon has partnered with STMicroelectronics for aid in its chip designs and to fabricate them in ST's 0.18-micron embedded EEPROM process, but Echelon product manager Mathew Chacko emphasized that ST will not serve as a second source.

Both of the new transceivers will be priced at $10 each in low volumes, but will be discounted significantly in OEM quantities. The PL 3120, packaged in a 38-lead TSSOP, will sample in February, with volume production slated for April. The PL 3150, in a 64-lead TQFP, will sample in June and be offered in volume in July.

For more information on this product go to www.echelon.com.

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