LSI Logic Aims ZSP500 at multimedia wireless

By Bernard Cole
iApplianceWeb
(09/24/02, 04:55:51 PM EDT)

Milpitas, Ca.--- Extending the portfolio of its ZSP digital signal processor (DSP) cores, LSI Logic Corp. has joined the rush to all things networked multimedia with its new ZSP500 for consumer multimedia and mobile applications.

Based on the ZSP second-generation G2 superscalar architecture, architectural innovations of the ZSP500 include an eight-stage pipeline, scalable program and data paths, and user-configurable memory architecture, enabling clock speeds of up to 400 MHz in 0.11-micron technology.

The addition of a richer instruction set produces better code density and a more efficient execution of key algorithms.

Keeping in mind the confined space, small footprint designs of most small footprint iappliances in the consumer and mobile space, the processor incorporates extensive embedded debugging capabilities including real-time profiling and an optional Embedded Trace Module (ETM) for advanced in-system multiprocessor hardware and software debugging.

The ZSP500 core also allows designers to incorporate customized instructions for their target application. Developers can differentiate by adding their own acceleration logic onto programmable, multi-processor platform for advanced multimedia and communications applications such as GPRS, CDMA2000, MPEG-4 and WLAN 802.11.

It is available for use as part of the company's RapidChip semiconductor platform for fast SoC designs.

For more information, go to http://www.lsilogic.com.